1. Field of the Invention
The present invention relates to a clock signal generating circuit, a semiconductor integrated circuit and a method for controlling a frequency division ratio, which allow changing frequency division ratios of clock signals outputted from a plurality of frequency dividing circuits to different frequency division ratios.
2. Description of the Related Art
With development of higher-speed and larger scale semiconductor integrated circuits in recent years, there are increasing demands for such semiconductor integrated circuits with lower power consumption. The power consumption of semiconductor integrated circuits increases proportionally to the operating frequency thereof. In response to such demands, Japanese Unexamined Patent Application No. 7(1995)-134701 describes a technology in which a semiconductor integrated circuit is provided with a plurality of internal buses. Built-in modules in the circuit are classified according to their individual operating speeds and are respectively connected to their corresponding internal buses for operation. In this manner, modules that need to operate at high-speeds and modules that do not need to operate at high-speeds are separated, thereby reducing power consumption.
In recent years, memories having a high-speed data transfer capability, such as double data rate memories including DDR/DDR2 SDRAMs, have been employed as external memories that operate in conjunction with the above-described type of semiconductor integrated circuits. However, there is a problem in employing this type of high-speed memory that the power consumption of the semiconductor integrated circuit increases if the semiconductor integrated circuit is operated at the operating frequency of the high-speed memory, while on the other hand, the high-speed memory does not operate normally if the high-speed memory is operated at the operating frequency of the semiconductor integrated circuit with the purpose of reducing power consumption.